1. Field of the Invention
The present invention relates to volatile semiconductor memory and, more particularly, volatile semiconductor memory with increased redundancy for a defective memory cell.
2. Description of Related Art
Recently, volatile semiconductor memory such as dynamic random access memory (DRAM) is widely used as memory incorporated into a mobile phone or the like. With a recent increase in the amount of data processed in equipment, a memory capacity increases accordingly. The large capacity memory includes a large number of memory cells, and each device needs to maintain a performance that meets specifications. It is, however, difficult to manufacture all of an enormous amount of memory cells within the range of specifications due to manufacturing variations in memory cells, crystal defects of a semiconductor substrate or dust which are inevitable in manufacturing, and so on.
In order for the memory to have redundancy for defects in memory cells, a spare memory cell is generally prepared to replace a defective memory cell. The memory cell which is determined to be defective by pre-shipment inspection may be replaced with a spare memory cell by using a fuse or the like. This enables shipment of normal memory. However, even with the use of this memory, thermal stress after shipment, such as heat due to soldering and use, aged deterioration and so on cause degradation of the performance of the memory cell, making the memory cell defective. In this case, the use of the spare memory cell cannot prevent defects.
DRAM stores data by accumulating charges in a capacitor. The accumulated charges, however, decrease with time due to leakage current. Therefore, DRAM refreshes to recharge the capacitor at certain time intervals (cell hold time). If the memory cell is degraded after shipment, DRAM can be unable to retain data in spite of refreshing due to increased leakage current.
An approach to overcome this drawback is to incorporate a circuit to add redundancy for a defective memory cell into DRAM so as to have redundancy for defects after shipment. An example of this circuit (memory cell redundant circuit) is disclosed in Japanese Unexamined Patent Application Publication No. 11-238393.
FIG. 12 shows DRAM 1000 of related art. In the DRAM 1000 shown in FIG. 12, BIST circuit 1001 performs self-test on a memory cell 1007 each time power is turned on, and then stores the address of the memory cell 1007 determined to be defective as a result of the self-test. FIG. 13 shows the flowchart of the self-test. In normal use state, the DRAM 1000 compares an address input from a logic circuit 1008 with the stored defective address. If, as a result of the comparison, the input address matches the defective address, the DRAM 1000 generates an address of a spare memory cell 1006 and uses the spare memory cell 1006 instead of the defective memory cell.
This configuration allows the performance of DRAM to meet the specifications with the use of the spare memory cell 1006 even if a defective memory cell occurs. Further, since the self-test is performed each time DRAM is powered-on, the DRAM can have redundancy for a defective memory cell after shipment as well.
However, it has now been discovered that the memory cell redundant circuit of related art needs to compare all the addresses supplied from a logic circuit in normal use state with the stored defective address, which causes a decrease in access speed. Further, the spare memory cell may be placed apart from other normal memories, and a long wiring also causes a decrease in access speed. Furthermore, it is necessary to prepare a spare memory cell in order to replace a defective memory cell, which causes an increase in chip area.